1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a clock synchronous semiconductor memory device for transferring data and taking in an external signal synchronously with a clock signal. Particularly, the invention relates to a structure of a data input/output section in a synchronous semiconductor memory device that operates in a DDR (Double Data Rate) mode of transferring data at both rising and fall edges of a clock signal. More particularly, the invention relates to a structure for operating the data input/output section at a rate faster than an external clock signal.
2. Description of the Background Art
In a high-speed data processing system, it is required to transfer data between a memory and a processor at high speed. As such a memory for transferring data at high speed, a clock synchronous semiconductor memory device to transfer data synchronously with a clock signal is known. Since data is transferred synchronously with a clock signal such as a system clock, the data transfer rate is determined by the clock signal and high-speed data transfer can be achieved.
In the clock synchronous semiconductor memory device, a control signal instructing an operation mode is merely required to satisfy the condition of set up and hold timings relative to the clock signal. It is unnecessary to consider a skew among control signals, and it is unnecessary to determine an internal timing in consideration of the margin for the skew among the control signals. Thus, the internal operation start timing can be set faster, and high speed access can be achieved.
Such a clock synchronous semiconductor memory device comes to be widely used. However, to achieve higher-speed data transfer, a semiconductor memory device operating in a DDR (Double Data Rate) mode of transferring data synchronously with both the rising and falling edges of a clock signal is implemented.
FIG. 81 is a timing chart representing a data reading operation of a conventional DDR mode semiconductor memory device. FIG. 81 shows an example of the data reading operation in the case where column latency CL is 2 and burst length BL is 4. The column latency denotes the number of clock cycles required for valid data to be output externally since a read command for instructing data reading operation is applied. The burst length indicates the number of input/output data successively per data terminal when one data reading/writing instruction is applied.
The read command for instructing data reading operation is applied synchronously with the rising edge, for example, of an external clock signal Ext.CLK. Internally, an internal clock signal CLKP is generated in response to the rising edge of external clock signal Ext.CLK, and an internal clock signal CLKN is generated synchronously with the falling edge of external dock signal Ext.CLK.
When the read command is applied, selection of a memory cell and reading of internal data are internally executed synchronously with an external clock signal. At this time, data of two bits is read in parallel per data output terminal. The 2-bit data read in parallel is converted to serial data in accordance with clock signals CLKP and CLKN, and the serial data is sequentially transferred.
Subsequently, an output circuit operates in response to an output clock signal CLKO generated synchronously with internal clock signals CLKP and CLKN, and produces external read data Dout from the internal read data. Since the column latency CL is 2 and the burst length BL is 4, after elapse of two clock cycles since the read command is applied, external read data Dout is produced, and data of four bits per data output terminal is successively output synchronously with output clock signals CLKO.
As shown in FIG. 81, in the case of the DDR mode, data is output synchronously with the rising and falling edges of external clock signal Ext.CLK, so that data can be transferred at a frequency twice as high as that of external clock signal Ext.CLK. Thus, data can be transferred at higher speed.
FIG. 81 shows a state where phases of internal clock signals CLKP and CLKN lead the rising and falling edges of external clock signal Ext.CLK. This is because internal clock signals CLKP and CLKN are generated from external dock signal Ext.CLK by using a DLL (Delay Locked Loop) for generating internal clocks CLKP and CLKN.
Output clock signal CLKO is generated in data reading, after elapse of column latency, synchronously with internal clock signals CLKP and CLKN.
FIG. 82 is a diagram schematically showing the configuration of a section of generating internal clock signals CLKP and CLKN. In FIG. 82, the internal clock generating section includes: edge detecting circuits 950 and 956 for detecting an intersection of complementary clock signals Ext.CLK and Ext.CLKB externally applied; one-shot pulse generating circuits 952 and 954 each for generating a one-shot pulse signal in response to the rising edge of an output signal of edge detecting circuit 950; and a one-shot pulse generating circuit 958 for generating a one-shot pulse signal in response to the rising edge of an output signal of edge detecting circuit 956.
Edge detecting circuits 950 and 956 each are formed of, for example, a differential amplifier, and perform complementary edge detecting operations to each other. Specifically, edge detecting circuit 950 outputs a signal which goes high when external dock signal Ext.CLK is higher than complementary external clock signal Ext.CLKB. Edge detecting circuit 956 outputs a signal which goes high when complementary external clock signal Ext.CLKB attains higher than external clock signal Ext.CLK.
One-shot pulse generating circuit 952 generates a one-shot pulse signal having a predetermined time width in response to the rising edge of the output signal of edge detecting circuit 950 and generates internal clock signal CLK. One-shot pulse generating circuit 954 generates clock signal CLKP for output control having a predetermined time width in the form of a one-shot pulse in response to the rising edge of the output signal of edge detecting circuit 950.
One-shot pulse generating circuit 958 generates clock signal CLKN for output control by generating a one-shot pulse signal having a predetermined time width in response to the rising edge of the output signal of edge detecting circuit 956.
FIG. 83 is a timing chart representing an operation of the internal clock generating section illustrated in FIG. 82. In FIG. 83, to make explanation simpler, it is assumed that the DLL is not provided and internal clock signals CLKP, CLKN, and CLKO are generated in accordance with external clock signals Ext.CLK and Ext.CLKB.
When external clock signal Ext.CLK becomes higher than external clock signal Ext.CLKB, edge detecting circuit 950 generates an H-level signal. Accordingly, one-shot pulse generating circuit 954 generates a one-shot pulse signal, and internal clock signal CLKP is generated. Therefore, internal dock signal CLKP is generated synchronously with the rising edge of external clock signal Ext.CLK and the falling edge of complementary external clock signal Ext.CLKB.
On the other hand, edge detecting circuit 956 outputs an H-level signal when external clock signal Ext.CLK goes low and complementary external clock signal Ext.CLKB goes high. One-shot pulse generating circuit 958 generates a one-shot pulse signal in response to the rising edge of an output signal of edge detecting circuit 956, to generate internal clock signal CLKN.
Therefore, internal clock signals CLKP and CLKN are generated synchronously with the rising and falling edges, respectively, of external clock signal Ext.CLK, so that their phases are shifted from each other by a half cycle of external clock signal Ext.CLK.
In data reading, under control of a not-shown reading control circuit, output clock signal CLKO is generated synchronously with internal clock signals CLKP and CLKN.
FIG. 84 is a diagram schematically showing the configuration of a data reading section. FIG. 84 schematically shows the configuration of the section for reading one-bit data. In FIG. 84, the data reading section includes: a register circuit 960 receiving internal read data RD0 and transferring the received data synchronously with an internal clock signal CLKEV; a register circuit 962 receiving internal read data RD1 and transferring the received data synchronously with an internal clock signal CLKOD; an output drive circuit 964 for transferring the data transferred from register circuits 960 and 962 externally, synchronously with output clock signal CLKO; and a multiplexer 965 for multiplexing internal clock signals CLKP and CLKN in accordance with an address signal bit A0 to generate internal read clock signals CLKEV and CLKOD.
In the semiconductor memory device, synchronously with internal clock signal CLK generated according to external clock signal Ext.CLK, reading of internal data (selection of a memory cell and amplification and transfer of internal read data) is performed. Internal read data RD0 and RD1 are transferred in parallel to register circuits 960 and 962. Multiplexer 965 generates internal read clock signals CLKEV and CLKOD from internal clock signals CLKP and CLKN in accordance with address signal bit A0. For example, when address signal bit A0 is “0”, according to internal clock signals CLKP and CLKN, internal read clock signals CLKEV and CLKOD are generated. In this case, therefore, internal read data RD0 stored in register circuit 960 is transferred first.
Output drive circuit 964 transfers data generated synchronously with internal clock signals CLKP and CLKN and transferred from register circuits 960 and 962 externally. Output clock signal CLKO is therefore generated synchronously with the rising and falling edges of external clock signal Ext.CLK, and external output data Dout is transferred at the rising and falling edges of external clock signal Ext.CLK.
As shown in FIG. 84, on the inside, the internal circuit is operated at the cycle of external clock signal Ext.CLK, to perform selection of a memory cell, transference of memory cell data, and then a so-called “parallel to serial conversion” for transference in the data reading section. In this way, the internal circuit can operate stably also for a high-speed clock signal, and data can be transferred externally at a period twice as short as that of the external clock signal.
A data writing section also has a configuration similar to that of the data reading section. A serial-to-parallel converting process of receiving data supplied synchronously with both the rising and falling edges of external clock signal Ext.CLK from the outside of the memory device, and transmission of internal write data to selected memory cells in parallel are performed. In data writing as well, therefore, the internal circuit operates in cycles of the external clock signal. Data supplied in the cycle twice as short as that of the external clock is received, and data can be written to the selected memory cells.
In the semiconductor memory device, a function test has to be carried out to assure the reliability of the product. In the case of performing the test, a tester (testing apparatus) has to generate a clock signal and apply it to a synchronous semiconductor memory device to be tested.
When the operating speed of the semiconductor memory device increases and the frequency of the clock signal becomes high, there is such a case that the tester cannot generate a required high-speed clock signal. Particularly, in the case where there is no large change in the contents of a test while the operating speed of the synchronous semiconductor memory device increases due to alteration of generations or the like, a higher-speed synchronous semiconductor memory device is tested by using the tester used for the synchronous semiconductor memory device of the previous generation, in order to reduce the cost of the test or for other reasons.
In such a case, in the semiconductor memory device, generally, the internal clock signal is generated synchronously with both the rising and falling edges of an external clock signal, and the internal circuit is operated in the cycle twice as short as that of the external clock signal.
Between the semiconductor memory device and the tester, data is transferred synchronously with a relatively low-speed external clock signal generated by the tester. For a semiconductor memory device with an SDR (Single Data Rate) mode of transferring data synchronously with the rising edge or falling edge of the external clock signal, an internal clock signal of a frequency twice as high as that of the external clock signal is generated to operate the internal circuit in synchronization of the internal clock signal, so that an actual operation of the internal circuit can be tested by using the low-speed tester.
However, in the semiconductor memory device with the DDR mode of transferring data synchronously with the rising and falling edges of the external clock signal, data input/output sections already operate at a frequency twice as high as that of the external clock signal. Even when the internal dock signal of a frequency twice as high as that of the external clock signal is generated, read clock signal CLKO shown in FIG. 83, for example, is similarly a clock signal of a frequency twice as high as that of the external clock signal. Even when the frequency of the external clock signal is internally multiplied to generate an internal clock signal having a doubled clock frequency, the data input/output section cannot be operated in the DDR mode at a frequency twice as high as the internal clock.
For example, in a signal waveform diagram of FIG. 83, when internal clock signal CLKP is generated synchronously with both the rising and falling edges of external clock signal Ext.CLK, internal clock signals CLKP and CLKN become the same clock signal, so that the internal circuit cannot be operated accurately. In addition, output clock signal CLKO merely turns signal having the same frequency as that of internal clock signal CLKP, and the input/output circuitry cannot be operated in the DDR mode.
In the semiconductor memory device with the SDR mode as well, in the case of generating the internal clock signal synchronously with both the rising and falling edges of the external clock signal, only the internal clock signal of the frequency twice as high as that of the external clock signal can be generated, and an even higher-speed internal clock signal cannot be generated.
In addition to a test such as a function test, stress acceleration cannot be accurately performed by operating a data input/output circuit at high speed in an acceleration test, and a problem such that time required to perform a stress acceleration test such as a burn-in becomes long occurs.